1. Field of the Invention
The present invention relates to a complementary metal oxide semiconductor integrated circuit (A complementary metal oxide semiconductor is hereinafter referred to as CMOS and an integrated circuit is hereinafter referred to as IC). Particularly, the present invention relates to a CMOS IC in which latch-up immunity for example is improved.
2. Description of the Prior Art
FIG. 1 is a plan view showing an example of a conventional CMOS static RAM (a random access memory). FIG. 2 is a cross-sectional view taken along the line II--II in FIG. 1. Referring to FIG. 1, a pair of N channel inverter transistors 11a and 11b, a pair of P channel load transistors 12a and 12b and a pair of N channel read-write access transistors 13a and 13b are formed in a memory cell shown by dotted lines. Accordingly, this memory cell is a 6-device static type memory cell. A word line 14 comprised of polysilicon, a power supply line 15 comprised of a p.sup.+ diffusion layer and a ground line 16 are connected to this memory cell. The word line 14 is connected to the gates of the transistors 13a and 13b. The drain regions 17a and 17b of the transistors 13a and 13b, respectively, are connected through a contact to a bit line of aluminum not shown. The power supply line 15 is connected to the drains of the transistors 12a and 12b.
Referring to FIG. 2, an N type well 22 is formed in a portion of a P type substrate 21. P.sup.+ diffusion regions 23a and 23b are formed on the surface of the N type well 22. The p.sup.+ diffusion region 23b forms the power supply line 15 shown in FIG. 1. N.sup.+ diffusion regions 24a and 24b are formed on the surfaces of other portions of the P type substrate 21. The n diffusion region 24a forms the drain region 17a of the transistor 13a and the n.sup.+ diffusion region 24b forms the source region 19a of the transistor 13a. On the surfaces of the P type substrate 21 and the N type well 22, separated oxide films 25a, 25b and 25c are formed in appropriate positions and polysilicon films 26a, 26b, 26c and 26d serving as gates or connections are also formed in appropriate positions. Gate oxide films 27 a and 27b are formed under the polysilicon films 26a and 26b, respectively. The polysilicon film 26b forms the word line 14 shown in FIG. 1.
FIG. 3 is a view showing a laminated structure formed between a power supply terminal and a ground terminal in the CMOS IC shown in FIGS. 1 and 2. Referring to FIG. 3, on the surfaces of the P type substrate 21 and the N type well 22, separation oxide films 35a, 35b and 35c and metallic connections 36a and 36b of aluminum or the like are formed. The metallic connection 36a serves as a power supply terminal and a power supply voltage Vcc is applied to this metallic connection 36a. The metallic connection 36b serves as a ground terminal and is connected to the ground. The metallic connection 36a is connected to the n.sup.+ diffusion region 34a serving as a region for making contact to the N type well 22 as well as to the p.sup.+ diffusion region 23b forming the power line 15 shown in FIG. 1. The metallic connection 36b, on the other hand, is connected to the n.sup.+ diffusion region 34b forming the ground line 16 shown in FIG. 1.
As described above, the conventional CMOS IC has a laminated structure as shown in FIG. 3 and accordingly a parasitic circuit as shown in FIG. 4 exists between the power supply and the ground. Referring to FIG. 4, the transistor 41 is an npn type transistor structured by the N type well 22, the P type substrate 21 and the n.sup.+ diffusion region 34b shown in FIG. 3 and the transistor 42 is a pnp type transistor structured by the p.sup.+ diffusion region 23b, the N type well 22 and the P type substrate 21. A resistor 43 is a parasitic resistor in the N type well 22 and a resistor 44 is a parasitic resistor in the P type substrate 21. A power supply terminal 45 corresponds to the metallic connection 36a in FIG. 3 and a ground terminal 46 corresponds to the metallic connection 36b in FIG. 3.
Thus, in a conventional CMOS IC, a parasitic circuit as shown in FIG. 4 exists between the power supply and the ground, which causes problems as set forth in the following. When a negative electric noise is applied to the N type well 22 (the base of the transistor 42) or when a positive electric noise is applied to the P type substrate 21 (the base of the transistor 41), a forward bias state is established between the emitter and the base of the transistor 42 or 41 and both the transistors 41 and 42 are conducted, causing a so-called latch-up phenomenon, namely, lowering of the potential of the power supply terminal 45. The circuit shown in FIG. 4 is in a structure in which conduction of the transistor 42 provokes conduction of the transistor 41 and vice versa.
In order to dissolve the above described problems, a method for improving latch-up immunity by improvement of a process technology of an IC has been proposed, as can be seen in "Latch-up Elimination in High Density CMOS" in page 54 of 1983 VLSI Symposium Digest. In this proposed method, however, parasitism of a circuit between the power supply and the ground as shown in FIG. 4 cannot be avoided and when a noise voltage becomes high, latch-up occurs unfavorably.